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19-0067; Rev 0; 2/05
KIT ATION EVALU E AILABL AV
HI-IF Single-Chip Broadband Tuners
General Description Features
Fully Integrated HI-IF Filter Fully Integrated VCOs, No External Components or Traces Low 8dB Noise Figure High Linearity--Greater Than 54dBc, CSO, CTB, X-MOD Industry's Smallest Footprint Superior Phase Noise for 256-QAM, 8-VSB, and COFDM
MAX3570/MAX3571/MAX3573
The MAX3570/MAX3571/MAX3573 low-cost, broadband, dual-conversion tuner ICs are designed for use in digital television receivers. Each IC integrates all necessary RF functions, including an integrated HI-IF filter, fully integrated VCOs, and an integrated IF VGA. The operating frequency range extends from 50MHz to 878MHz while providing over 60dB RF/IF gain-control range. The MAX3570/MAX3571 have an IF frequency centered at 44MHz, while the MAX3573 has an IF output centered at 36MHz. These devices include a variable-gain front-end, achieving an overall 8dB noise figure. A dual synthesizer generates both local oscillator (LO) frequencies, providing superior phase noise performance of -86dBc/Hz at 10kHz. The integrated HI-IF filter achieves 55dBc (typ) of image rejection. Only an IF SAW filter, passive loop filters, and a crystal are needed to complete a single-chip tuner. Device programming and configuration are accomplished with a 3-wire serial interface for the MAX3570, and with a 2-wire serial interface for the MAX3571/MAX3573. The MAX3570/MAX3571/MAX3573 are available in a 48-pin QFN-EP package and are specified for the commercial (0C to +70C) temperature range.
Ordering Information
PART MAX3570CGM MAX3571CGM MAX3573CGM TEMP RANGE 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 48 QFN-EP* 48 QFN-EP* 48 QFN-EP*
*EP = Exposed paddle.
Applications
LNABIAS
Pin Configurations/ Functional Diagrams
IFOUT2+ IFOUT2RFVGA IFVGA BIAS VCC IFINGND IFIN+
38
DVB-C Digital Terrestrial Receivers ATSC Digital Terrestrial Receivers Cable Modems
VCC 1
48
47
46
45
44
43
42
VCC
41
40
39
VCC
37 36 IFOUT135 IFOUT1+ 34 GND 33 VCC 32 GND 31 VCC 30 TUNE2 29 LOCFLT2 28 GND 27 VCC 26 CPOUT2 25 VCC 24
DOCSIS/EURO DOCSIS Cable Modems ITU J.83 Digital Set-Top Boxes
RFIN+ 2 RFIN- 3 GND 4 VCC 5 GND 6 VCC 7
MAX3570
HI-IF FILTER
Selector Guide
PART MAX3570 MAX3571 MAX3573 SERIAL INTERFACE 3-Wire 2-Wire 2-Wire IF CENTER FREQUENCY (MHz) 44 44 36
TUNE1 8 LOCFLT1 9 GND 10 I.C. 11 CS 12 13 14 15 16 17 18 19 20 21 22 23 3-WIRE SERIAL INTERFACE DUAL SYNTHESIZER
OSCOUT
DIV/LD
OSCIN
SDA
I.C.
CPOUT1
GND
Pin Configurations/Functional Diagrams continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
GND
GND
VCC
SCL
VCC
HI-IF Single-Chip Broadband Tuners MAX3570/MAX3571/MAX3573
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +5.5V IFIN_, IFOUT1_, IFOUT2_, RFIN_, TUNE_, LOCFLT_, CPOUT_, OSCIN, OSCOUT, IFVGA, RFVGA, BIAS, LNABIAS, ADDR_, CS, SCL, SDA, DIV/LD...............-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin QFN (derate 27mW/C above +70C) ............2162mW Operating Temperature Range...............................0C to +70C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
CAUTION! ESD SENSITIVE DEVICE
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(MAX357_ EV kit, VCC = +4.75V to +5.25V, RBIAS = 5.9k 1%, no AC signal applied, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +5.0V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SUPPLY VOLTAGE AND SUPPLY CURRENT Supply Voltage Supply Current RF and IF VGA Input Bias Current RF and IF VGA Control Voltage LOGIC INTERFACE Input-Logic Low (VIL) Input-Logic High (VIH) Input Logic Current Output-Logic Low Output-Logic High Sink current = 3mA Source current = 3mA 2.8 2.3 -10 +10 0.4 0.9 V V A V V At TA = +25C, VRFVGA = +3.0V At TA = +70C, VRFVGA = +0.5V VRFVGA = VIFVGA = +0.5V and +3.0V Maximum gain Minimum gain -50 3 0.5 4.75 320 385 +50 5.25 V mA A V CONDITIONS MIN TYP MAX UNITS
2
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HI-IF Single-Chip Broadband Tuners
AC ELECTRICAL CHARACTERISTICS
(MAX357_ EV kit, VCC = +4.75V to +5.25V, RBIAS = 5.9k 1%, inputs terminated to 75, fRFIN = 50MHz to 878MHz, fIF = 45.75MHz (MAX3570/MAX3571), fIF = 38.9MHz (MAX3573), fCOMP1 = 1MHz, fCOMP2 = 62.5kHz, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +5.0V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Operating Frequency Range Input Return Loss Voltage Gain Gain-Reduction Range Gain Flatness Noise Figure CONDITIONS Gain specification met across this frequency band Worst case across band, 75, any RFVGA setting ZSOURCE = 75, ZLOAD = 200, VRFVGA = +3.0V Measured at 50MHz VRFVGA = +3.0V at fRFIN = 878MHz vs. 50MHz VRFVGA = 0.5V at fRFIN = 878MHz vs. 50MHz VRFVGA = +3.0V VRFVGA = +3.0V, TA = +25C to +70C, VCC = 4.85V to 5.15V, fRF = 860MHz At 12dB gain reduction, TA = +25C to +70C, VCC = 4.85V to 5.15V, fRF = 860MHz VRFVGA = +3.0V, TA = +25C to +70C, VCC = 4.85V to 5.15V At 12dB gain reduction, TA = +25C to +70C, VCC = 4.85V to 5.15V Beats within Output Channel Flatness Isolation 0dBmV PIX carrier level (Note 2) From PIX to (PIX + 4) MHz 5MHz to 150MHz, RF input to IF output (Note 3) Measured at 91MHz above desired PIX (MAX3570/MAX3571) Image Rejection Measured at 77.75MHz above desired PIX (MAX3573) Spurious at RF Input (Note 3) 50MHz to 878MHz Above 878MHz (LO and LO harmonics) fOFFSET = 1kHz Single Sideband Phase Noise Output Return Loss fOFFSET = 10kHz, BWLOOP = 2.5kHz fOFFSET = 100kHz, BWLOOP = 2.5kHz Balanced, 50 -62 -86 -105 9 dB dBc/Hz 50 55 -54 -48 +3 dBmV -0.5 -63 50 TA = +25C TA = +70C 31.5 30.0 30 -1.5 -2 7.9 34 dBm 52.5 +8 dBm +18 -48 +0.3 -68 55 dBc +1.0 dBc dB dBc +1.5 +2 MIN 50 8 38.5 37 45.0 43.5 TYP MAX 878 UNITS MHz dB dB dB dB dB
MAX3570/MAX3571/MAX3573
OVERALL REQUIREMENTS (RF INPUT TO 1st IF OUTPUT)
IIP2
IIP3
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3
HI-IF Single-Chip Broadband Tuners MAX3570/MAX3571/MAX3573
AC ELECTRICAL CHARACTERISTICS
(MAX357_ EV kit, VCC = +4.75V to +5.25V, RBIAS = 5.9k 1%, inputs terminated to 1k, ZLOAD = 300, fIF = 40MHz to 48MHz, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +5.0V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SECOND IF STAGE Input Impedance Output Impedance Passband Voltage Gain Passband Flatness Maximum Output Voltage VGA Gain Slope -3dB Bandwidth Noise Figure Noise Figure vs. Attenuation IIP3 OIP3 PSRR VIFVGA = +3.0V to +0.5V (Note 3) fIF = 44MHz, VIFVGA = +3.0V First 10dB back-off Gain = 45dB, VOUT = 1.5VP-P Gain = 27dB, VOUT = 1.5VP-P VOUT = 1.5VP-P, VIFVGA = +3.0V to +0.5V (Note 3) 50mVP-P at 200kHz 5.1 0.3 -27.5 -11.3 25 -57 10 Balanced Balanced (Note 3) ZSOURCE = 1.1k, ZLOAD = 300, VIFVGA = +3.0V VIFVGA = +0.5V From PIX to (PIX - 4) MHz for 45.75MHz PIX frequency (Note 3) 3.2 20 180 50 53 14.5 1.7 100 57 23 0.2 k dB dB VP-P dB/V MHz dB dB/dB dBm dBm dB CONDITIONS MIN TYP MAX UNITS
4
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HI-IF Single-Chip Broadband Tuners
SYNTHESIZER ELECTRICAL CHARACTERISTICS
(MAX357_ EV kit, VCC = +4.75V to +5.25V, RBIAS = 5.9k 1%, fCOMP1 = 1MHz, fCOMP2 = 62.5kHz, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +5.0V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER 1st LOCAL OSCILLATOR (LO1) Tuning Range VCO Tuning Gain 1st LOCAL OSCILLATOR (LO1) DIVIDER RF1 N-Divider Ratio RF1 R-Divider Ratio 1st LOCAL OSCILLATOR (LO1) PHASE DETECTOR AND CHARGE PUMP Phase-Detector Phase Noise Charge-Pump Source/Sink Matching Charge-Pump Tri-State Current 2nd LOCAL OSCILLATOR (LO2) Tuning Range VCO Tuning Gain 2nd LOCAL OSCILLATOR (LO2) DIVIDER RF2 N-Divider Ratio RF2 R-Divider Ratio 2nd LOCAL OSCILLATOR (LO2) PHASE DETECTOR AND CHARGE PUMP Phase-Detector Phase Noise Charge-Pump Source/Sink Matching Charge-Pump Tri-State Current fOFFSET = 2kHz (Note 3) Correlate locked vs. unlocked RF2 -7 -142 6 +7 dBc % nA 512 2 65,535 127 1175 25 1193 70 MHz MHz/V fOFFSET = 2kHz (Note 3) Correlate locked vs. unlocked RF1 -7 -142 6 +7 dBc % nA 256 1 8191 31 1274 40 2111 120 MHz MHz/V CONDITIONS MIN TYP MAX UNITS
MAX3570/MAX3571/MAX3573
LOGIC INTERFACE
(MAX357_ EV kit, VCC = +4.75V to +5.25V, RBIAS = 5.9k 1%, TA = 0C to +70C, unless otherwise noted.) (Note 1)
PARAMETER Maximum Clock Frequency CONDITIONS MIN 400 TYP MAX UNITS kHz
Note 1: These parameters are production tested from TA = +25C to +70C, and are guaranteed by design and characterization at TA = 0C. Note 2: When using the tuning table provided in the EV kit documentation. Note 3: These parameters are guaranteed by design and characterization, and are not production tested.
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5
HI-IF Single-Chip Broadband Tuners MAX3570/MAX3571/MAX3573
Typical Operating Characteristics
(MAX357_ EV kit, VCC = +5.0V, RBIAS = 5.9k, fRF = 860MHz, fIF = 44MHz (MAX3570/MAX3571), 36MHz (MAX3573), TA = +25C, unless otherwise noted.)
VOLTAGE GAIN vs. RFVGA VOLTAGE
MAX3570/71/73 toc01 MAX3570/71/73 toc02
SUPPLY CURRENT vs. TEMPERATURE
400 50 40 VOLTAGE GAIN (dB) 30 20 10 0 320 MAXIMUM GAIN -10 -20 25 30 35 40 45 50 55 60 65 70 0 0.5
VOLTAGE GAIN vs. SUPPLY VOLTAGE
MAX3570/71/73 toc03
40
380 SUPPLY CURRENT (mA)
39 VOLTAGE GAIN (dB)
50MHz
450MHz
360 12dB ATTENTUATION 340
38 850MHz 37
300 TEMPERATURE (C)
36 1.0 1.5 2.0 2.5 3.0 4.75 4.85 4.95 5.05 5.15 5.25 RFVGA VOLTAGE (V) SUPPLY VOLTAGE (V)
VOLTAGE GAIN vs. FREQUENCY (MAX GAIN)
MAX3570/71/73 toc04
VOLTAGE GAIN vs. FREQUENCY (MAX -12dB)
MAX3570/71/73 toc05
NOISE FIGURE vs. FREQUENCY
MAX3570/71/73 toc06
41 40 VOLTAGE GAIN (dB) 39 38 37 36 35 34 50 250 450 FREQUENCY (MHz) 650 TA = +70C TA = +25C TA = +55C
29 28 VOLTAGE GAIN (dB) 27 26 25 24 TA = +70C 23 22 TA = +25C TA = +55C
10.0 9.5 NOISE FIGURE (dB) 9.0 8.5 8.0 7.5 TA = +25C 7.0 TA = +70C
TA = +55C
850
50
250
450 FREQUENCY (MHz)
650
850
50
250
450 FREQUENCY (MHz)
650
850
NOISE FIGURE vs. VOLTAGE GAIN
MAX3570/71/73 toc07
PHASE NOISE vs. OFFSET FREQUENCY
-60 -70 PHASE NOISE (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 -30
MAX3570/71/73 toc08
IFOUT1 FREQUENCY RESPONSE
MAX3570/71/73 toc09
20 18 TA = +70C NOISE FIGURE (dB) 16 14 12 10 8 29 31 33 35 37 TA = +55C TA = +25C
-50
10
0 AMPLITUDE (dB)
MAX3570/MAX3571
-10 MAX3573 -20
39
-150 100 1k 10k 100k 1M 10M FREQUENCY (Hz)
-40 0 50 100 150 IF FREQUENCY (MHz)
VOLTAGE GAIN (dB)
6
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HI-IF Single-Chip Broadband Tuners
Typical Operating Characteristics (continued)
(MAX357_ EV kit, VCC = +5.0V, RBIAS = 5.9k, fRF = 860MHz, fIF = 44MHz (MAX3570/MAX3571), 36MHz (MAX3573), TA = +25C, unless otherwise noted.)
MAX3570/MAX3571/MAX3573
RFIN INPUT RETURN LOSS
MAX3570/71/73 toc10
INPUT IP2 vs. VOLTAGE GAIN
MAX3570/71/73 toc11
INPUT IP3 vs. VOLTAGE GAIN
MAX3570/71/73 toc12
-7.5
60 55 INPUT IP2 (dBm) 50 TA = +70C 45 40 35 TA = +55C TA = +25C
28
-8.0 RETURN LOSS (dB)
23 INPUT IP3 (dBm) TA = +55C 18 TA = +25C
-8.5
13
-9.0
8
TA = +70C
-9.5 50 250 450 650 850 RF FREQUENCY (MHz)
30 19 24 29 VOLTAGE GAIN (dB) 34 39
3 19 24 29 VOLTAGE GAIN (dB) 34 39
IFVGA VOLTAGE GAIN vs. IFVGA VOLTAGE
MAX3570/71/73 toc13
IFVGA VOLTAGE GAIN vs. IF FREQUENCY
MAX3570/71/73 toc14
IFVGA NOISE FIGURE vs. IFVGA VOLTAGE
MAX3570/71/73 toc15
60 55 IFVGA VOLTAGE GAIN (dB) 50 45 40 35 30 25 20 15 10 0.3 0.8 1.3 1.8 2.3 2.8
58 56 IFVGA VOLTAGE GAIN (dB) 54 52 50 48 46 44 42 40 TA = +55C TA = +70C TA = +25C
30
25 NOISE FIGURE (dB)
20 TA = +70C 15 TA = +55C
10
TA = +25C
5 1 10 100 1000 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 IFVGA VOLTAGE (V) IF FREQUENCY (MHz)
3.3
IFVGA VOLTAGE (V)
IFVGA INPUT IP3 vs. IFVGA VOLTAGE
MAX3570/71/73 toc16
-5 -10 -15 -20 -25 -30 -35 -40 0.3 0.8 1.3 1.8 2.3 2.8 TA = +25C TA = +70C
INPUT IP3 (dBm)
TA = +55C
3.3
IFVGA VOLTAGE (V)
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HI-IF Single-Chip Broadband Tuners MAX3570/MAX3571/MAX3573
Pin Description
PIN 1 2, 3 4, 6, 10, 20, 23, 24, 28, 32, 34, 45 5 7 8 9 11 12 13 14 15 16 17 18 19 21 22 25 26 NAME VCC RFIN+, RFINFUNCTION RF Variable-Gain Amplifier (VGA) Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches. Differential LNA Inputs. Requires AC coupling and can be driven balanced or single-ended. Recommend driving pin 3 and AC ground pin 2 for optimum input IP2 performance.
GND
Ground. Connect to PC board ground plane.
VCC VCC TUNE1 LOCFLT1 I.C. ADDR2 CS ADDR1 SCL SDA VCC DIV/LD I.C. CPOUT1 VCC OSCOUT OSCIN VCC CPOUT2
1st Mixer Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches. 1st VCO Circuitry Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches. 1st VCO Tuning Input. Connect this analog voltage input to a third-order loop-filter output. 1st LO Noise-Filtering Capacitor Connection. Connect a capacitor to GND. (Refer to the EV kit.) Internal Connection. Leave this pin unconnected (MAX3570). 2-Wire Serial Interface 2nd Address Pin (MAX3571/MAX3573) 3-Wire Serial Interface Enable Input Pin (SPITM/QSPITM/MICROWIRETM Compatible) (MAX3570) 2-Wire Serial Interface 1st Address Pin (MAX3571/MAX3573) 3-Wire Serial Interface Clock Input Pin (SPI/QSPI/MICROWIRE Compatible) (MAX3570) 2-Wire Serial Interface Clock Input Pin (MAX3571/MAX3573) 3-Wire Serial Interface Data Input Pin (SPI/QSPI/MICROWIRE Compatible) (MAX3570) 2-Wire Serial Interface Data Input Pin (MAX3571/MAX3573) Digital Circuitry Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches. Divider or Lock-Detect Logic Output Internal Connection. Leave this pin unconnected. 1st PLL Charge-Pump Output. Connect this high-impedance current output to a third-order loop-filter input. 1st Synthesizer Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches. Reference Oscillator Buffered Output Reference Oscillator Input. Connect an external reference oscillator or crystal to this analog input through a coupling capacitor. 2nd Synthesizer Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches. 2nd PLL Charge-Pump Output. Connect this high-impedance current output to a third-order loop-filter input.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. 8 _______________________________________________________________________________________
HI-IF Single-Chip Broadband Tuners
Pin Description (continued)
PIN 27 29 30 31 33 35, 36 37 38, 39 40 41 42, 43 44 NAME VCC LOCFLT2 TUNE2 VCC VCC FUNCTION 2nd Charge-Pump Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches. 2nd LO Noise-Filtering Capacitor Connector. Connect a capacitor to GND. (Refer to the EV kit.) 2nd VCO Tuning Input. Connect this analog voltage input to a third-order loop-filter output. 2nd VCO Circuitry Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches. 2nd LO Generation Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches.
MAX3570/MAX3571/MAX3573
IFOUT1+, 1st Differential IF Outputs. These outputs are AC-coupled to the SAW filter inputs. IFOUT1VCC IFIN+, IFINIFVGA VCC 2nd Mixer and 1st IF Amplifier Circuit Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches. Differential IF Inputs. Connected to the SAW filter outputs. IF VGA Control. See the Typical Operating Characteristics. IF VGA Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches.
IFOUT2+, IF VGA Outputs IFOUT2VCC HI-IF Filter Circuit Supply Voltage. Bypass with a capacitor as close to the pin as possible. Do not share the bypass capacitor ground vias with any other branches. Bias Resistor Connection. Connect a 5.9k precision 1% resistor to GND. Resistor value can be increased to decrease the nominal current at the expense of linearity. Refer to Application Note: MAX3570/MAX3571/MAX3573 Bias Resistor Setting for further information. RF VGA Control. See the Typical Operating Characteristics. LNA Bias Input. Connect through an inductor to GND. (Refer to the EV kit.) Exposed Ground Paddle. DC and AC GND return for the IC. Connect to PC board ground plane using multiple vias.
46 47 48 EP
BIAS RFVGA LNABIAS GND
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9
HI-IF Single-Chip Broadband Tuners MAX3570/MAX3571/MAX3573
Detailed Description
Programmable Registers
The MAX3570/MAX3571/MAX3573 include nine programmable registers (registers 1-9) consisting of six divider registers (registers 1-6), one VCO control register (register 7), and one test register (register 8). The final register (register 9) controls the HI-IF filter frequency offset, as well as the DIV/LD output MUX status. Most registers contain some don't care (X) bits. These can be either a "0" or a "1" and do not affect the mode of operation (Table 1). Data is shifted in MSB first. Positive logic is used.
2-Wire Serial Interface
The MAX3571/MAX3573 use a 2-wire I2C*-compatible serial interface. The serial bus is monitored continuously, waiting for a START condition followed by its address. The address has 5 MSB internally set, while the next two bits are set with external pins, ADDR2 and ADDR1. The LSB determines whether it is a read or write. When the device recognizes its address, it acknowledges by pulling the SDA line low for one clock period; it is then ready to accept the register address for the first byte of data. Another acknowledge (ACK) is sent once the register address is received. The device is then ready to accept the data byte. More data bytes can be sent for sequential registers, and ACK is sent after each byte. After the final ACK is sent, the master issues a STOP condition to free the bus. Figure 2 shows the details of the 2-wire interface structure. There is only one read-back register in the MAX3571/MAX3573. To access it, send a START condition, and then the read address is set by the external ADDR2 and ADDR1 pins. An ACK is sent, and the master then begins to read from the slave. After the eight bits have been read, the master should issue a noacknowledge (NACK), and then a STOP condition.
3-Wire Serial Interface
The MAX3570 uses a 3-wire SPI/QSPI/MICROWIREcompatible serial interface. An active-low chip select (CS) enables the device to receive data from the serial input (SDA). Register address and data information are clocked in on the rising edge of the serial clock signal (SCL). While shifting in the serial data, the device remains in its original configuration. A rising edge on CS latches the data into the MAX3570's internal register, initiating the device's change of state. Figure 1 shows the details of the 3-wire interface address and data configuration.
Figure 1. 3-Wire Serial Interface Address and Data Configuration
MSB 4 ADDRESS BITS A3 A2 A1 A0 D7 D6 D5 8 DATA BITS D4 D3 D2 D1 D0 LSB
Figure 2. 2-Wire Serial Interface Register Write Example
START DEVICE ADDRESS 8b110000 ACK REGISTER ADDRESS 8b0000XXXX ACK DATA D7-D0 ACK DATA D7-D0 ACK STOP
Figure 3. 2-Wire Serial Interface Register Read Example
START DEVICE ADDRESS 8b110001 ACK READ BYTE (8 Bits) 8bXXXXXXXX NACK STOP
Table 1. 2-Wire Serial Interface Address Configuration (Set by ADDR2 and ADDR1)
*Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
ADDRESS (WRITE/READ) C0/C1hex C2/C3hex C4/C5hex C6/C7hex ADDR2 Low Low High High ADDR1 Low High Low High
10
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HI-IF Single-Chip Broadband Tuners MAX3570/MAX3571/MAX3573
Table 2. Register Configuration
MSB REGISTER NUMBER 1 2 3 4 5 6 7 8 9 REGISTER NAME VCO1_N1 VCO1_N2 VCO1_R VCO2_N1 VCO2_N2 VCO2_R VCO_SET TEST HI-IF REGISTER ADDRESS D7 00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex X 1N7 X 2N15 2N7 X 1VCO2 X X D6 X 1N6 X 2N14 2N6 2R6 1VCO1 1T4 X D5 X 1N5 X 2N13 2N5 2R5 1VCO0 1T3 F1 8 DATA BITS D4 1N12 1N4 1R4 2N12 2N4 2R4 X 1T2 F0 D3 1N11 1N3 1R3 2N11 2N3 2R3 1CP1 1T1 MUX3 D2 1N10 1N2 1R2 2N10 2N2 2R2 1CP0 1T0 MUX2 DB1 1N9 1N1 1R1 2N9 2N1 2R1 2CP1 ST1 MUX1 D0 1N8 1N0 1R0 2N8 2N0 2R0 2CP0 ST0 MUX0 LSB
X = Don't care.
Table 3. Register Description
REGISTER NUMBER 1 2 3 4 5 6 7 8 9 REGISTER NAME VCO1_N1 VCO1_N2 VCO1_R VCO2_N1 VCO2_N2 VCO2_R VCO_SET TEST HI-IF REGISTER ADDRESS 00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex VCO1 N-divider high VCO1 N-divider low VCO1 R-divider VCO2 N-divider high VCO2 N-divider low VCO2 R-divider VCO select and charge-pump settings Test mode. For test purposes only. Program to 20hex. Mode select, MUX output select FUNCTION
Table 4. 1st VCO N-Divider Higher Register (VCO1_N1)
BIT ID X 1N BIT NAME X 1st VCO N-Divider BIT LOCATION (0 = LSB) 7, 6, 5 4-0 Reserved 1st VCO N-divider MSB bits FUNCTION
Table 5. 1st VCO N-Divider Lower Register (VCO1_N2)
BIT ID 1N BIT NAME 1st VCO N-Divider BIT LOCATION (0 = LSB) 7-0 FUNCTION 1st VCO N-divider LSB bits
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HI-IF Single-Chip Broadband Tuners MAX3570/MAX3571/MAX3573
Table 6. 1st VCO R-Divider Higher Register (VCO1_R)
BIT ID X 1R BIT NAME X 1st VCO R-Divider BIT LOCATION (0 = LSB) 7, 6, 5 4-0 Reserved 1st VCO R-divider FUNCTION
Table 7. 2nd VCO N-Divider Higher Register (VCO2_N1)
BIT ID 2N BIT NAME 2nd VCO N-Divider BIT LOCATION (0 = LSB) 7-0 FUNCTION 2nd VCO N-divider MSB bits
Table 8. 2nd VCO N-Divider Lower Register (VCO2_N2)
BIT ID 2N BIT NAME 2nd VCO N-Divider BIT LOCATION (0 = LSB) 7-0 FUNCTION 2nd VCO N-divider LSB bits
Table 9. 2nd VCO R-Divider Higher Register (VCO2_R)
BIT ID X 2R BIT NAME X 2nd VCO R-Divider BIT LOCATION (0 = LSB) 7 6-0 Reserved 2nd VCO R-divider FUNCTION
Table 10. VCO Tank and Charge-Pump Select Register (VCO_SET)
BIT ID BIT NAME BIT LOCATION (0 = LSB) FUNCTION 1st VCO Tank Select: * 000 = 1st VCO tank (the lowest frequency oscillator) * 001 = 2nd VCO tank * 010 = 3rd VCO tank * 011 = 4th VCO tank * 100 = 5th VCO tank * 101 = 6th VCO tank * 110 = 7th VCO tank * 111 = 8th VCO tank (the highest frequency oscillator) Reserved 1st VCO Charge-Pump Current: * 00 = 0.2mA * 01 = 0.4mA * 10 = 0.6mA * 11 = 0.8mA 2nd VCO Charge-Pump Current: * 00 = 0.2mA * 01 = 0.4mA * 10 = 0.6mA * 11 = 0.8mA
1VCO
1st VCO Tank Select
7, 6, 5
X
X
4
1CP
1st VCO Charge-Pump Current
3, 2
2CP
2nd VCO Charge-Pump Current
1, 0
12
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HI-IF Single-Chip Broadband Tuners MAX3570/MAX3571/MAX3573
Table 11. HI-IF Step Control and MUX Output Register (HI-IF)
BIT ID X BIT NAME X BIT LOCATION (0 = LSB) 7, 6 Reserved HI-IF Filter Control: * 00 = Step down 5MHz * 01 = Nominal * 11 = Step up 5MHz Lock-Detect and MUX Output Control: * 0000 = Normal, low-noise operation * 0001 = Lock detect for the 1st VCO * 0010 = Lock detect for the 2nd VCO * 0011 = 1st VCO N-divider * 0100 = 1st VCO R-divider * 0101 = 2nd VCO N-divider * 0110 = 2nd VCO R-divider * 0111 = Reference oscillator * 1000 = AND output of lock detector * 1001 = NAND output of lock detector * 1010 = 1st VCO VTUNE over/under indicator * 1011 = 2nd VCO VTUNE over/under indicator FUNCTION
F
HI-IF Filter Control
5, 4
MUX
Lock-Detect and MUX Output Control
3-0
Table 12. Read Mode Register Configuration
MSB REGISTER NUMBER 1 REGISTER NAME D7 LD_POR LOCK1 D6 LOCK2 D5 POR 8 DATA BITS D4 OU1 D3 OU2 D2 X DB1 X D0 X LSB
Table 13. Read Mode Register Description
REGISTER NUMBER 1 REGISTER NAME LD_POR FUNCTION Lock detect and power-on reset
Table 14. Lock Detect and POR Register
BIT ID LOCK1 LOCK2 POR OU1 OU2 X BIT NAME LOCK1 LOCK2 POR OU1 OU2 X BIT LOCATION (0 = LSB) 7 6 5 4 3 2, 1, 0 Lock indicator for 2nd VCO Power-on reset indicator; 1 indicates successful power-on reset Over or Under VTUNE indicator for 1st VCO (see Table 15) Over or Under VTUNE indicator for 2nd VCO Reserved FUNCTION Lock indicator for 1st VCO (see Table 15)
Table 15. 1st VCO Truth Table
LOCK1 1 0 0 OU1 x 0 1 DESCRIPTION 1st VCO locked (Under) Choose next lower tank (Over) Choose next higher tank
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13
HI-IF Single-Chip Broadband Tuners MAX3570/MAX3571/MAX3573
Typical Application Circuit
IF OUTPUT TO ADC FROM DAC
FROM DAC
LNABIAS
IFOUT2+
IFOUT2-
RFVGA
IFVGA
BIAS
IFIN-
GND
IFIN+
38
VCC
VCC
48 VCC RFIN+ RF INPUT RFINGND VCC GND VCC TUNE1 LOCFLT1 GND 1 2 3 4 5 6 7 8 9 10
47
46
45
44
43
42
41
40
39
VCC
37 36
IFOUT1-
MAX3570
35 34 HI-IF FILTER 33 32 31 30 29 28 DUAL SYNTHESIZER 27 26 25
IFOUT1+ GND VCC GND VCC TUNE2 LOCFLT2 GND VCC CPOUT2 VCC
I.C. 11 CS 12
3-WIRE SERIAL INTERFACE
13
14
15
16
17
18
19
20
21
22
23
24
DIV/LD
CPOUT1
OSCOUT
OSCIN
SCL
GND
SERIAL INTERFACE
14
______________________________________________________________________________________
GND
GND
SDA
VCC
I.C.
VCC
HI-IF Single-Chip Broadband Tuners
Applications Information
RF Input
An LNA provides a single-ended broadband input matched to a 75 source. It provides a linear, continuous gain-control range of over 30dB before the signal is upconverted. A 16nH inductor in series with a 1000pF capacitor is required at the RF input (pin 3) to achieve optimal matching (see the Typical Application Circuit).
Synthesizer Comparison Frequency Selection
The two on-chip synthesizers of the MAX3570/MAX3571/ MAX3573 are capable of supporting a wide range of comparison frequencies. The PLL for the first LO (LO1) provides a comparison frequency range from below 250kHz up to 4MHz, assuming a 4MHz reference (crystal) frequency. The second LO (LO2) PLL supports a comparison frequency range from below 50kHz up to 2MHz, again assuming a 4MHz reference. Comparison frequencies of 1MHz for LO1 (R1 = 4) and 250kHz for LO2 (R2 = 16) are recommended for the MAX3570 and MAX3571. For the MAX3573, the recommended LO2 comparison frequency is 142.8571kHz (R2 = 28, 4MHz crystal frequency). These values ensure optimum resolution while working with the loop filters to suppress spurious energy and provide acceptable lock time.
MAX3570/MAX3571/MAX3573
HI-IF Frequency Agility
In a double conversion receiver, beat frequencies are generated from harmonics of the LOs associated with this system. In some instances these beat frequencies may coincide with the IF. If this occurs, it is possible to shift the HI-IF slightly by retuning the LOs. This shift moves the beat out of the IF band. The MAX3570/ MAX3571/MAX3573 support this capability by allowing the user to shift the center frequency of the HI-IF filter slightly, tracking the shift in the LO frequencies, preserving the optimum image rejection and insertion loss. The HI-IF filter frequency shift is controlled with the HIIF filter step control bits (F0 and F1, register address 8). (Patent pending.)
Synthesizer Loop Filters
A third-order lowpass loop filter is used for each local oscillator to achieve low spurious and low phase noise. The loop bandwidth is chosen so the spurious rejection is sufficient and a reasonable lock time is achieved. Refer to the EV kit for the recommended loop-filter component values.
IF Outputs
A first differential IF output (IFOUT1+, IFOUT1-), although intended to drive a standard IF SAW filter, is capable of driving loads as low as 200. A second differential IF output (IFOUT2+, IFOUT2-) provides a balanced output capable of driving loads as low as 300 and can be AC-coupled to a standard QAM demodulator's ADC.
Crystal Oscillator Interface
The crystal oscillator pins (OSCIN, OSCOUT) must be connected to a crystal or an external reference oscillator. When connecting directly to a crystal, refer to the EV kit for the recommended component values. When using an external reference oscillator, drive OSCIN with an amplitude of 1.5VP-P, and leave OSCOUT unconnected.
Gain Control
The MAX3570/MAX3571/MAX3573 have two VGA circuits that are used to achieve the optimum SNR while minimizing distortion. At low input signal levels the RFVGA voltage should be 3.0V. This sets the LNA gain at its maximum. The IFVGA control voltage is used to set the required output signal level. As the RF input level increases, the IFVGA voltage drops. When the IFVGA voltage reaches a user-defined value (RFVGA attack point), the IFVGA voltage is frozen and the RFVGA voltage is adjusted to maintain the desired output level.
Power-Supply Layout
To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at a central VCC node. The VCC traces branch out from this node, each going to a separate V CC node in the MAX3570/MAX3571/ MAX3573 circuit. At the end of each trace is a bypass capacitor with a low impedance to ground at the frequency of interest. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor for a low-inductance ground connection.
VCO1 Selection
VCO1 generates the first local oscillator (LO1) frequency for the upconverting mixer. It consists of an array of eight VCOs; each tuned to a unique frequency band, to cover the required frequency range. The desired VCO is chosen through the serial data interface (SDI). Please refer to Application Note: MAX3550/MAX3551/ MAX3553 VCO Selection for further information on VCO1 VCO selection.
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15
HI-IF Single-Chip Broadband Tuners MAX3570/MAX3571/MAX3573
Pin Configurations/ Functional Diagrams (continued)
LNABIAS IFOUT2+ IFOUT2RFVGA IFVGA BIAS VCC VCC IFINGND IFIN+ VCC
Matching Network Layout
The layout of a matching network can be very sensitive to parasitic circuit elements. To minimize parasitic inductance, keep all traces short and place components as close to the IC as possible. To minimize parasitic capacitance, a cutout in the ground plane (and any other planes) below the matching network components can be used. Refer to the EV kit for the recommended input matching network.
48 VCC 1 RFIN+ 2 RFIN- 3 GND 4 VCC 5 GND 6 VCC 7 TUNE1 8 LOCFLT1 9 GND 10 ADDR2 11 ADDR1 12 13
47
46
45
44
43
42
41
40
39
38
37 36 IFOUT1-
MAX3571 MAX3573
HI-IF FILTER
35 IFOUT1+ 34 GND 33 VCC 32 GND 31 VCC 30 TUNE2 29 LOCFLT2 28 GND DUAL SYNTHESIZER 27 VCC 26 CPOUT2 25 VCC
Chip Information
TRANSISTOR COUNT: 18,970 PROCESS: SiGe BiCMOS
2-WIRE SERIAL INTERFACE
14
15
16
17
18
19
20
21
22
23
24
OSCOUT
DIV/LD
OSCIN
SDA
I.C.
CPOUT1
GND
16
______________________________________________________________________________________
GND
GND
VCC
SCL
VCC
HI-IF Single-Chip Broadband Tuners
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Refer to G4877-1.
32, 44, 48L QFN.EPS
MAX3570/MAX3571/MAX3573
PACKAGE OUTLINE 32,44,48L QFN, 7x7x0.90 MM
21-0092
H
1
2
U
PACKAGE OUTLINE, 32,44,48L QFN, 7x7x0.90 MM
21-0092
H
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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